1. The Field of the Invention
The present invention relates to semiconductor devices and methods for their construction. More particularly, the present invention relates to hardening of gate oxides in MOS semiconductor devices by nitrogen implantation without formation of ion depletion regions in polysilicon. More specifically, the present invention provides a method for obtaining regions of substantial nitrogen concentrations at the gate oxide interface without having a corresponding area of substantial nitrogen concentration in bulk polysilicon.
2. The Background Art
Gate oxide hardening is required for at least three reasons. First, insufficiently hard gate oxides can break down at voltages below normal operating voltages. Second, hardened gate oxides resist hot electron degradation which creates dangling bonds. Finally, hardened gate oxides are especially effective in preventing boron diffusion from the polysilicon gate electrode. This is particularly important in PMOS devices where boron is commonly provided in the polysilicon and must be prevented from diffusing through the gate oxide into the silicon substrate to minimize threshold voltage fluctuation.
Hardening has gained increasing significance since the reduced size of current semiconductor devices has correspondingly compressed gate oxide thickness. Dopant diffusion from polysilicon into the silicon substrate has become an important problem because of the increasingly thin gate oxide regions found in modern semiconductor devices. For example, in some next generation devices the channel length will be about 0.18 .mu.m and the gate oxide thickness will be about 30 .ANG.. In future generation devices both the channel length and gate oxide thickness will continue to shrink. Thus, gate oxide hardening will be an important process in the construction of modern semiconductor devices for the foreseeable future.
Typically, hardening has been accomplished by diffusing nitrogen into gate oxide after formation. In this process, the gate oxide is thermally grown on a single crystal silicon substrate. Next, the gate oxide is exposed to an atmosphere containing nitrous oxide or nitric oxide at about 900.degree. C. which causes silicon nitride and silicon oxynitride formation at the gate oxide-silicon substrate interface. The increased concentration of nitrogen containing species at the gate oxide-silicon substrate interface prevents boron diffusion into the silicon substrate, hot electron degradation and improves the breakdown resistance of the gate oxide.
Unfortunately, hardening through nitrogen diffusion has certain deficiencies. First, the high temperature of gate oxide hardening by nitrogen diffusion obliterates any sharp concentration profiles at the previously implanted dopant region interfaces. Furthermore, gate oxide by nitrogen diffusion hardening fails to prevent boron diffusion into the gate oxide from polysilicon although it does prevent boron diffusion from the gate oxide to the silicon substrate. The dielectric properties of the gate oxide are adversely affected by electronically active dopants such as boron.
A nitrogen implantation process in which nitrogen ions are implanted into polysilicon gate electrode cures some of the deficiencies in the nitrogen diffusion gate oxide hardening process (S. Haddad, et al., EKE Electron Device Letter, 8, 58-60, 1987; T. Kuroi, et al., Tech. Dig. of IEDM, 325-328, 1993; S. Nakayama et al., 1996 Symposium on VLSI Technology, 228-229; A. Chou, et al., International Reliability Physics Symposium, 174-177, 1997). The above-mentioned references are herein incorporated by reference.
FIG. 1 illustrates central features of a nitrogen implanted MOS device (Chou et al., 1997). Curve 2 represents the nitrogen distribution profile after implantation and shows that nitrogen is concentrated at a peak region 5 in the polysilicon. Curve 4 represents the nitrogen distribution profile after annealing and shows that nitrogen is concentrated at the silicon substrate-gate oxide interface (peak 7) and the gate oxide-polysilicon interface (peak 9). The region of significant nitrogen concentration at the gate oxide-polysilicon interface prevents boron diffusion from polysilicon into the gate oxide.
However, as can be seen in Curve 4 of FIG. 1 and is more clearly illustrated in FIG. 2 a significant nitrogen concentration peak exists in the bulk polysilicon gate electrode after annealing. Referring now to FIG. 2, Curves 12 and 14 represent the nitrogen and the boron distribution profiles respectively in the bulk polysilicon after nitrogen implantation and annealing at 850.degree. C. Similarly, Curves 18 and 16 represent the nitrogen and the boron distribution profiles respectively in the bulk polysilicon after nitrogen implantation and annealing at 950.degree. C.
Examination of FIG. 2 shows that the size of the nitrogen peaks 15 and 17 in bulk polysilicon inversely affects the boron concentration profile near the gate oxide interface. The left side of the graph (x=0.00) corresponds to the top of the polysilicon gate and the right side corresponds to the polysilicon-gate oxide interface as indicated by the nitrogen concentration peak. The larger the nitrogen peak in the bulk polysilicon, the lower the boron concentration in the polysilicon proximate the polysilicon-gate oxide interface.
Retardation of boron diffusion in the bulk polysilicon results in formation of polysilicon depletion regions during device operation. Polysilicon depletion regions act as non-conductive areas that effectively increase gate oxide thickness, thus degrading device performance.
In any event, it has become apparent that as device sizes shrink an improved technique for hardening gate oxides is required. Such improved techniques should harden gate oxide without forming polysilicon depletion areas at the gate oxide-polysilicon interface.